One of the terms referring to the performance of NVMe SSDs that you have heard the most in recent months is SLC Cache. That is why we have prepared this article for you so that you can understand how it works and what benefits it brings to the performance of our high-performance solid-state drives.

Data storage based on NAND Flash technology has resulted in a paradigm shift in various sectors of computing, from memory cards for handheld devices to NVMe SSDs on PCs. It is precisely in the latter case that one of the historical bottlenecks in history has been eliminated by not having the limitations in both access latency and bandwidth of traditional hard drives, however, there is no perfect technology that perform at 100% and there are always elements that weigh it down, forcing engineers to have to find and implement solutions.

NAND Flash and memory cells

NAND Flash memory is a type of NVRAM or non-volatile RAM, this means that its operation is the same as a conventional RAM, but with the difference that its data is not lost when the system stops receiving power. The trade-off for having this ability is having a limited number of memory writes in its life cycle. Although the advantages in the form of performance when it comes to accessing storage are worth it, not in vain, every computer system is only as fast as its slowest part, which is usually storage, leaves it.

Each bit of memory in a RAM memory is stored in what are called memory cells and in the first NAND Flash memories used for SSD storage, one bit per cell was used, which made storage very expensive. The solution? That each cell can hold data of 2 bits ( MLC ), 3 bits ( TLC ) or up to 4 bits ( QLC ). The added problem? The more bits per cell, the faster they degrade and therefore less useful life. Keep this in mind because it is the basis for understanding SLC Cache.

TLC and QLC cells don’t just degrade in duration

Once you have reached this point, many of you will have the idea in your head that NAND Flash memories of the MLC, TLC and QLC type have more storage capacity, although less duration, but the bandwidth of all of them is the same and therefore the type of cell does not vary the performance. Well, let us tell you that the bad news does not end there, but that the access speed also degrades.

When the CPU makes a request for access to a memory address in the NVMe SSD, it is received by the flash controller that will search for the data in memory to transmit it through the PCI Express or SATA interface, depending on which one you use. the unit, but the flash controller accesses the unit’s NVMe chips directly to manipulate its data and does not do so through the interfaces that we have mentioned.

The way to store the data in the NAND Flash memory is through changes in the voltage, an SLC memory only needs 1 voltage, an MLC requires 3 , but a TLC goes to 7 and if we go to a QLC the thing is goes to 15 . Well, the higher the number, the longer it takes to perform a read and write operation. And when does this start to be a problem? Well, from the TLC memory and if you look at the number of NVMe SSD units in the stores, you will see that they all use these cells at least today.

The solution: SLC cache

The first thing to keep in mind is that the SLC cache is not the same as the DRAM cache that is also in some NVMe SSDs, since we are not talking about the volatile memory that is between the flash controller and the PCI interface. Express of the same, since the SLC cache is also in the DRAM-Less units. In general, although there are exceptions that we will see later, within each NVMe chip there are two types of NAND Flash memory:

• A TLC or QLC memory for data storage
• A much smaller SLC memory that serves as a cache.

The first thing we have to understand is that a cache is nothing more than a memory much closer to a processor and therefore with lower latency that temporarily stores data. If we review what we have told you, we have the following premises:

• SLC cells have a much longer lifespan than TLCs and even longer than QLCs, so they take much longer to degrade.
• The access speed of SLC cells is much higher.

Thus, the solution is for the data to be temporarily dumped into the SLC memory, which functions as a buffer cache so that a data copy mechanism then modifies the memory addresses in the TLC.

SLC cache performance

We come to the most important part, the SLC cache has a fixed size and this means that, if we use it to send or receive small data, its performance will be maintained, but if for example we want to make a sequential copy of data in the form of a very large data block as soon as the SLC is full the performance will drop.

That is why, despite the fact that we can have two NVMe SSDs in our hands with the same storage, access interface and even cell types, that is, practically the same, they may have completely different performance. The reason? Obviously the SLC cache which can differ in size.

The SLC cache is not only used to store data with sequential access, but also random and it must be taken into account that programs when accessing information do so with high recursion and in a delimited block of information.

SLC cache types

There are two ways to manage the SLC cache, which will depend on the algorithm for this that the manufacturer has implemented in the flash controller. Rather, it refers to how much space within it can be allocated for temporary storage.

• In the static cache the storage space is fixed and cannot vary in size.
• In the dynamic cache the allocated size is variable.

How is dynamic cache possible if the number of SLC cells is fixed? The catch is to use the NVMe TLC cells as if they were SLCs, that is, make them store one bit in each instead of 3. So there are some NVMe chips that reallocate part of the storage as cache.

The advantage of the dynamic cache is that the size of the SLC cache is not exhausted, but there is a risk that more and more TLC cells are no longer used for storage, affecting the overall capacity of this to store data. For this reason, most dynamic SLC cache systems make use of systems that limit the maximum size of this through the firmware.